As computer and other digital systems become more complex and more capable, methods and hardware to enhance the transfer of data between system components or elements continually evolve. Data to be transferred include signals representing data, commands, or any other signals. System components or elements can include different functional hardware blocks on a single integrated circuit (IC), or on different ICs. The different ICs may or may not be on the same printed circuit board (PCB). System components typically include an input/output (IO) interface, or physical layer, specifically designed to receive data from other system components and to transmit data to other system components.
In many systems, some components are characterized as hosts and other components are characterized as clients. Host components generally include more capability or “intelligence” implemented, for example, as integrated circuit logic. An example of a host-client relationship is a memory controller (host)-memory device (client) relationship. It is often desirable for a client device, such as a dynamic random access memory (DRAM) for example, to include only a minimum amount of intelligence for functions such as managing IO. One reason for this is that it is expensive in terms of area and speed to implement logic on a DRAM device. Therefore, it is desirable for the host device to include as much intelligence as possible for managing IO interactions with a client such as a DRAM.
Existing IO interfaces and methods include “symmetrical 10” and “asymmetrical IO”. In general, for symmetrical IO, a host and a client each include similar IO capability, typically in the form of physical layer circuitry devoted to IO functions. Symmetrical IO can be expensive for the reasons explained above. For example, including all of the required physical layer IO logic in a DRAM is expensive.
In general, for asymmetrical IO, a host and a client do not have similar IO capability. The host typically includes at least some circuitry to manage IO on behalf of the client so that the client can be a simpler device. However, typical current asymmetrical physical layer IO designs place excessive burden on host side, for example by including circuitry for handling client functions.
Regardless of the type of IO interface, transferred data must be synchronized between host and client for proper operation. Synchronization includes accounting for or compensating for several phenomena that potentially cause errors, including signal jitter and bit skew. The phenomena include differences between component clocks, and physical attributes of the data paths that create noise and affect the integrity of the transferred signal. Current asymmetrical IO designs can have circuitry in the host device for performing this synchronization on behalf of both the host and client. Some of the circuitry is redundant. For example, the redundant circuitry includes phase interpolators for each of the host and client that adjust the phase of a sampling clock or a data signal in response to phase detection information. An object of this phase adjustment is to maintain the active edge, or sampling edge, of the sampling clock close to the center of the data eye of the data to be sampled in order to prevent errors. Client-side phase information is transferred from the client to the host, and used by the host-side synchronization circuitry to perform phase adjustment for the client device.
Another disadvantage of current asymmetrical IO systems is that client-side phase information is inefficiently transferred from the client device to the host device. For example, in some systems, dedicated pins are added to carry phase information for each data bit, which adds expense and undesirably increases form factors of components in the system.
FIG. 1 is a block diagram of portions of a prior art asymmetrical IO system 100, including a physical layer of a host device 102 and a physical layer of a client device 104. The host device 102 and the client device 104 each receive a system timing signal in a respective phase lock loop (PLL) (host PLL 116 or client PLL 106) to generate one or more local clock signals, including a sampling clock for sampling incoming data. The client device 104 receives data on multiple bidirectional data lines 112 and includes client phase detection circuitry 110 that determines whether the sampling clock is aligned close to the center of the data eye of the received data. The client phase detection circuitry outputs phase information that is transmitted to the host device 102 through physical signal carrier 114, which could be dedicated data lines.
The host device 102 includes host phase detection circuitry 118 that determines whether the local sampling clock is properly aligned with respect to data received by the host device 102 on multiple bidirectional data lines 112. The host device 102 also includes redundant circuitry for adjusting the phase of its local sampling clock, and for adjusting the phase of the data transmitted to the client device 104 in response to the client phase information transmitted on lines 114. In various prior systems, lines 114 represent dedicated, additional wires, circuit board traces, pins, etc. for each data bit transmitted on lines 112. For adjusting the phase of the host device local sampling clock, the host device 102 includes receive phase control logic 120, receive phase interpolator 122 and latch/flop 128. To adjust the phase of the data transmitted to the client device 104, the host device 102 includes transmit phase control logic 126, transmit phase interpolator 124, transmit phase control logic 126, and latch/flop 130.